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Cell-Based ASICs

CB-90


Technology
node
Max.
available
gates
Max. I/Os (MHz) Delay time
(F/O=2, L=0., 2-input NAND)
90 nm 100,000K 2800 10.2 ps

Description

Based on NEC Electronics’ 90 nm UX6 process technology, the CB-90 ASIC design platform is designed for a wide range of low-power, high-performance applications such as broadband communications equipment, high-end computing and storage systems, and mobile computing devices.

Features


Multiple Cell-Based Libraries

To address the specific needs of a broad spectrum of ASIC designs requiring high performance and low power, NEC Electronics has developed three different cell-based libraries and IP within the CB-90 ASIC family. Each library is developed to provide the performance and features required of their target application.


  CB-90L CB-90M
Master name µPD809000 µPD808000
Technology 90 nm CMOS process
Power supply voltage Internal 1.2 V 1.0 V
I/O block 3.3 V or 2.5 V
Mountable gates (minimum step)*1 5 M gates
Mountable gates (maximum step)*1 100 M gates
Maximum system frequency 200 MHz 366 MHz
Power consumption *2 2.7 nW/MHz/gates 1.8 nW/MHz/gates
Memory (capacity) 1-port SRAM 2 to 128 bits, 8 words to 16 K words
2-port (1R+1W) SRAM 2 to 128 bits, 8 words to 512 words
2-port (1RW+1RW) SRAM 2 to 128 bits, 128 words to 8 K words
ROM 2 to 128 bits, 128 words to 16 K words

*1

The mountable gates are the maximum number of usable gates (average value) when mounting only logic gates on the chip. This number can vary greatly depending on the circuit configuration and the types and number of mounted cores.

*2

Operation rate: 0.35

 
 

Documentation


Please use our
Tech Support Form
if you wish to request copies of ASIC documentation.
 
  Product Data Design Manuals
 
  Narrow Block Libraries
 
  Wide Block Libraries
 


 

Related Information


 
    Process Technologies Overview  
    Standard CMOS UX6  
    Standard CMOS UX5  


CB-90 Packaging Options

NEC Electronics offers a variety of ball grid array packaging configurations for CB-90 customers to support a broad number of applications. Click here for a list of supported packages.

IP Lineup

Within the CB-90 family, NEC Electronics offers a wide range of IP cores and high-performance I/Os. In addition to SRAM memory macros, NEC Electronics offers embedded DRAM macros from 4Mb to 16Mb in various configurations. Click here for more information on featured IP cores.

High Integration, High Speed and Low Power Consumption

NEC Electronics' CB-90 family is built on the advanced UX6 microfabrication process to achieve high integration and support for up to 100 million usable gates. High clock speeds are possible because of 1-volt, high-speed CMOS transistors that realize ultra-low power using a gate length of 60 nm, all-copper wiring and low-k (k = 2.9) inter-metal dielectrics.

The use of up to nine levels of all-copper wiring (minimum wiring pitch of 0.28 µm) in the CB-90 libraries enables both increased density and higher reliability. Moreover, the use of low-resistance copper material enables NEC Electronics to realize thinner wiring layers, contributing to higher speed and lower power consumption due to reduced wire capacitance.

Low gate-leakage is achieved by combining a radical nitridation process, which lowers the leakage current of the gate oxidized film, and a triple-oxide process that forms MOS transistors with three different gate-oxidized film thickness. Mixing optimum transistors according to the target circuit performance lowers power consumption by approximately 40% compared to power consumption of previous generations. The use of low-power techniques including a multi-power-supply design flow and automatic voltage control technology further reduces power consumption.

Using cells with low standby-leakage prevents the usual increase in leakage that accompanies a smaller geometry process and reduces leakage to the few µA required for backup operations at the chip level. Also, in normal operation at 1.0 volts, using high-density cells in circuits that perform high-speed signal processing increases speed and reduces power consumption. The combination of low standby-leakage high-density cell libraries and unique low-power design techniques enables NEC Electronics to realize sophisticated power management in its system LSI devices.

 
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