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EMMA2L   (µPD61120A,    µPD61122)

LSI for Low end Digital STB




Overview

The powerful and single-chip EMMA2L (µPD6121x) decoders for digital STBs and iDTVs integrate all of the elements required to design low-cost, entry-level Pay TV systems for the worldwide DVB markets. With a number of feature variants that provide cost-optimized solutions for Free-To-Air and various Pay TV applications, the devices use the second-generation Enhanced Multimedia Architecture (EMMA2) platform that delivers an industry-leading price/performance ratio. These decoders are aimed at low-end STB/FTA converter and IDTV markets that are moving toward analog switch-off.


Target System

  • Low-end STBs and iDTVs

Product Specification

Product Specification
On-chip CPU
  • Integrated high performance CPU : MIPS32® 4Kc® Core x 2
  • Main CPU : for Application, RTOS, API, BIOS
    • 225 MIPS at 187 MHz / 200 MIPS at 167 MHz
    • MIPS™ I, MIPS™ II instruction set architectures; subset of MIPS™ III
    • Cache size : I-Cache 8 KBytes, D-Cache 8 KBytes (Cache accessing for 2 ways)
  • Sub CPU : for MPEG decoder inside F/W (Audio/Video decode, AV-sync)
    • 225 MIPS at 187 MHz / 200 MIPS at 167 MHz
    • MIPS™ II instruction
    • Cache size : I-Cache 8 KBytes, D-Cache 8 KBytes, Scratch Pad 8 KBytes
Memory I/F
  • Unified Memory I/F : for CPU Work area, MPEG decode, Display, Graphics
    • DDR-SDRAM (x 16-bit Bus)
    • fMAX= 133 MHz frequency
    • Total 16-MByte/32-MByte/64-MByte/128-MByte area
  • External ROM I/F : for CPU object code, data area
    • Normal, page, and burst ROM support
    • NOR, NAND, and Strata flash ROM support
    • Total 64-MByte address area (max.)
    • 4-pair chip select signals
MPEG Stream Processor
  • NEC Electronics original processor core for software architecture
  • One parallel port or one serial port for stream input
  • Multiple CA & De-Scrambling
    • DVB de-scrambling include
    • Multi2 support
  • MPEG2-TS, MPEG2-DSS support
  • Maximum bit rate : 100 Mbits/sec
  • 40-PID filters (Video PID x1, Audio PID x2, PCR PID x1, PID x36)
  • 32-section filters (8-Byte/16-Byte depth)
  • High Speed Data port output for IEEE1394 I/F
MPEG Video Decoder
  • MPEG2 MP at ML x1 decoding support
  • MPEG2/1 elementary stream accepts
  • IDCT accelerator for JPEG decoding
  • I-flame still video decoding support
Audio Decoder
  • MIPS32 4Kc core : 200 MIPS at 167 MHz / 166 MIPS at 138 MHz
  • MPEG1/MPEG2 layer 1, 2 decoding support
  • Dolby® Digital 5.1-ch decoding support
    (Family option ; Output is down-mixed to L/R)
  • PCM L/R audio output
  • SPDIF with IEC60958 output (Dolby® Digital can be passed through to SPDIF)
  • Test-tone and mixing
Bit-Blt Graphics engine
  • 2-D image data transferring
  • Color space conversion (RGB32 to YCbCr 4:2:2) for OSD stretch
  • Color expansion
Display
  • Handle 5-graphics planes
    • Back ground plane x1
    • Live video plane x1 (4:2:0, 4:2:2)
    • Still video plane x1 (4:2:0, 4:2:2)
    • OSD plane x2 (1, 2, 4, 8 bpp + RGB15, 16, 32)
  • 256-level alpha blending among 5-planes
  • Real time scaling for live video and still video planes
    • x1/4 to x4 both H and V
  • Anti-flicker filter for OSD plane
Video Encoder
(for Analog TV)
  • NTSC, PAL, and SECAM format support
  • Supported Closed Caption, Teletext, WSS, CGMS, Video ID, and VPS
  • 6-DACs for CBVS & Y & C & RGB or YCbCr/YPbPr video output
  • Copy Guard (Only µPD61122)
  • ITU-R BT.656 digital output support
Peripherals
  • Standard UART x2
  • UART (16550 compatible) with 16-byte FIFO x2
  • Smart Card Interface x2
  • I2C port x2
  • IEEE1284 Interface
  • Timers
    • Two system, elapse, day, Watch Dog Timers
    • Four timers supporting input capture timers and output compare timers
  • CSI (Clocked Serial Interface) support
  • General PIO
  • Software Modem Interface support
  • IR Transmitter, and IR Receiver
Process
  • 0.15 µm CMOS process
Power supply voltage
  • VDD : Internal 1.5 V, I/O 3.3 V



Block Diagram

Block Diagram


Product Lineup

Order Number Package Package Code
µPD61120F1-100-JN1 272-pin plastic FBGA (21 x 21 mm) P272F1-100-JN1
µPD61122F1-100-JN1 272-pin plastic FBGA (21 x 21 mm) P272F1-100-JN1




This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.



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