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EMMA2   (µPD61130A,    µPD61132A), EMMA2+   (µPD61133,    µPD61135), EMMA2+S   (µPD61135)

LSI for Digital Set Top Box with HDD interface




Overview

The highly integrated, single-chip EMMA2 (µPD6113x) decoders for digital STBs (with HDD interfaces) and iDTVs have a number of variants to provide the most cost-effective solution for various Pay TV markets as well as Free-To-Air applications. The devices use the second-generation Enhanced Multimedia Architecture (EMMA2) that features a totally unified memory system. Significant performance improvements in the new architecture enable increased integration and reduced system cost while delivering better graphics and interactivity.
Although similar to the µPD61130 and µPD61132 decoders, the µPD61133 and µPD61135 devices offer more features and performance enhancements.


Target System

  • Personal Digital Video Recorders
  • IDTVs

Product Specification

Product Specification
Integrated High Performance CPU
  • NEC Electronics MIPS® VR4120A Core
    for application, RTOS, API, BIOS, and inside F/W
  • 200 MIPS at 167 MHz / 160 MIPS at 133 MHz
  • MIPS16™ ISA support
  • Cache size : I-Cache 16 KBytes, D-Cache 8 KBytes
Memory I/F
  • Unified Memory I/F : for CPU work area, MPEG decode, Display, Graphics
    • SDR-SDRAM (x 32-bit Bus)
    • fmax : 133 MHz frequency
    • Total 64-MByte area (max)
  • External ROM I/F : for CPU object code, data area
    • Normal, page, and burst ROM support (x 8/16-bit Bus)
    • Total 32-MByte address area (max)
MPEG Stream Processor
  • 3-TS Demux processing simultaneously
  • Support DVB, DirecTV stream (EMMA2)
  • MPEG2-TS (Transport Stream)
  • Maximum bit rate : Total 180 Mbits/sec, 100 Mbits/sec for each stream
  • 102-PID filters (Video PID x2, Audio PID x2, PCR PID x2, PID x96)
  • 192-section filters
  • High Speed Data port output for IEEE1394 Interface
  • 3DES function (EMMA2+)
MPEG Video Decoder
  • MPEG2 MP at ML decoder supports dual simul-SD decode for PIP or 2 TVs
  • I-frame still video decoding support
Audio Decoder
  • NEC Electronics original DSP core
  • MPEG1/MPEG2 Layer 1, 2 decoding support
  • Dolby® Digital 5.1ch decoding support (Family Option)
  • MP3 decoding support (Family Option)
  • PCM audio output
  • SPDIF with IEC60958 output
  • Test-tone and mixing
Transport Stream Recording
  • 2-Record & 1-Playback for PVR
  • Support Ultra DMA 33/66 (ATA-I/F)
  • Support Copy-Protection
Graphics Engine
  • Bit-Blt Graphics engine
  • 2D/1D image data transferring
  • H/V Resizing Filter
  • Color Space Conversion for OSD stretch
Display
  • Handle 8-graphics planes
    • Back ground plane x2
    • Live video plane x3
      Select from 4 planes ;
      MPEG2 Video 4:2:0 x2, Still 4:2:0/4:2:2 x1, and External Video In 4:2:2 x1
    • OSD plane x2 (2, 4, 8 bpp + RGB16, 32)
    • H/W Cursor plane x1 (1, 2, 4 bpp)
  • 256-level alpha blending among 6-planes
  • Anti-flicker filter for OSD plane
Support Digital Video Capture
  • ITU-R BT.656 Digital Input
Video Encoder
(for Analog TV)
  • NTSC, PAL, and SECAM format support
  • Supported Closed Caption, Teletext, WSS, CGMS, and Video ID
  • 6-channel DAC for simultaneous CVBS, YC, and RGB/YCbDr analog output
  • Copy Guard (Family option, only µPD61132A and µPD61135)
  • ITU-R BT.656 digital output support
PCI Interface
  • PCI Rev.2.1 Interface (3.3-V I/F, 32-bit 33 MHz Initiator/Target)
Peripherals
  • Standard UART x2
  • FUART (16550 compatible) with 16-Byte FIFO x2
  • Smart Card Interface x2
  • I2C port x2
  • CSI (Clocked Serial Interface) support
  • IEEE1284 Interface
  • Timers
    • Two system, elapse, day, Watch Dog Timers
    • Four timers supporting input capture timers and output compare timers
  • General PIO
  • Software Modem Interface support
Process
  • 0.15 µm CMOS process
Power Supply Voltage
  • Internal 1.5 V, I/O 3.3 V



Block Diagram

Block Diagram


Product Lineup

Order Number Package Package code Remark
µPD61130AS1-100-F6 352-pin plastic BGA (35 x 35 mm) Y352S1-127-F6-4
µPD61132AS1-100-F6 352-pin plastic BGA (35 x 35 mm) Y352S1-127-F6-4
µPD61133S1-100-F6 352-pin plastic BGA (35 x 35 mm) Y352S1-127-F6-4
µPD61135S1-100-F6 352-pin plastic BGA (35 x 35 mm) Y352S1-127-F6-4
µPD61133F1-100-KA2-A 389-pin plastic FBGA (22 x 22 mm) T.B.D Lead-free product
µPD61135F1-100-KA2-A 389-pin plastic FBGA (22 x 22 mm) T.B.D Lead-free product
µPD61133F1-100-KA2-Y 389-pin plastic FBGA (22 x 22 mm) T.B.D High-thermal-resistance product
µPD61135F1-100-KA2-Y 389-pin plastic FBGA (22 x 22 mm) T.B.D High-thermal-resistance product




This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.



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