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Products > Digital AV LSI > MPEG Decoder for STB > MPEG4(H.264) >

EMMA3SV   (µPD61300,    µPD61303)

High Performance MPEG Decoder LSI for Integrated Digital Television


Overview Target System Product Specification Block Diagram Product Lineup


Overview

The EMMA3SV (µPD61300, µPD61303) decoders embed video display functions and all of the necessary functions for reception of digital broadcasts, including audio and video digital signal decoding, into one single-chip solution.

EMMA3SV decoders can process the leading-edge H.264 video format, in addition to advanced audio standards such as Dolby® Digital Plus and HE-AAC, and offer on-chip USB and Ethernet connectivity for overall system cost reduction. These devices are ideal for televisions and STBs in Europe, Russia, India, and Brazil, where the H.264 format is gaining popularity.


Target System

  • H.264 iDTVs, STBs
  • IPTV in STB or integrated TV

Product Specification

Product Specification
Integrated high-performance CPU
  • MIPS32™ 24KEc™ CPU
  • 470 MIPS at 327 MHz
  • 16 KB instruction cache; 16 KB data cache
Unified memory interface
  • DDR2 memory interface
  • 16-, 32-bit bus
  • 32 to 256 MB total memory
  • 2.6 GB/s bandwidth
  • Flash ROM interface
  • 64 MB total address area
  • 8-, 16-bit bus
MPEG transport stream processing engine
  • Four dedicated transport stream input ports: two serial and two parallel
  • MPEG2-TS (DVB) format
  • 36 PID filters
  • 32 section filters
MPEG video decoder
  • MPEG2 MP@ML, MP@HL, H.264/AVC HP@L4.0, MP@L4.0, 3.2, and VC-1 AP@L3, L2 formats
Audio controller
  • MPEG-1/2 L1/2, MPEG4 AAC, MPEG4 HE-AAC, DD, DD+, MP3, and WMA formats
  • SPDIF output
  • 5.1-ch output
Graphics and display engine
  • 2DBitBlt
  • Six graphics planes (five main planes and one sub-plane)
  • 256-level alpha-blending function
  • Real-time video scaling (1/4 to 8/1 H/V) x2
Video decoder
  • Two D/A converters for analog Y/C and CVBS video output
  • PAL, SECAM and NTSC formats
  • ITU-R BT.656 and BT.1120 digital output
USB 2.0 interface
  • Compliant with EHCI specification
  • High (480 Mbps), full (12 Mbps), and low speeds (1.5 Mbps)
Ethernet interface
  • Integrated Ethernet MAC conforming to IEEE 802.3/3u/3x
  • Compliant with RMII (10 Mbps/100 Mbps Ethernet) specification
Peripherals
  • Two-channel FUART
  • One-channel UART
  • Two-channel SmartCard interface
  • Two-channel I2C interface
  • Clocked serial interface
  • Two-channel IR receiver; IR blaster
  • Watchdog timer, real-time clock
Package
  • 559-pin plastic BGA



Block Diagram

Block Diagram


Product Lineup

T.B.D



This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.


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